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 FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
September 2001 Revised August 2003
FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
General Description
This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1048 can be paired with its companion driver, the FIN1047, or any other LVDS driver.
Features
s Greater than 400Mbs data rate s Flow-through pinout simplifies PCB layout s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Pin compatible with equivalent RS-422 and LVPECL devices s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number FIN1048M FIN1048MTC Package Number M16A MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name RIN1+, RIN2+, RIN3+, RIN4+ RIN1-, RIN2-, RIN3-, RIN4- EN EN VCC GND Description Non-Inverting LVDS Inputs Inverting LVDS Inputs Driver Enable Pin Inverting Driver Enable Pin Power Supply Ground ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs
Function Table
Inputs EN H H H X L or Open
H = HIGH Logic Level Z = High Impedance
Outputs RIN+ H L X X ROUT- L H X X ROUT H L H Z Z
EN L or Open L or Open H X
L or Open Fail Safe Condition
L = LOW Logic Level X = Don't Care Fail Safe = Open, Shorted, Terminated
(c) 2003 Fairchild Semiconductor Corporation
DS500588
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FIN1048
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Input Voltage (VOUT) DC Output Current (IO) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) ESD (Human Body Model) ESD (Machine Model) 260C
-0.5V to +4.6V -0.5V to +4.6V -0.5V to 6V
16 mA
Recommended Operating Conditions
Supply Voltage (VCC) Magnitude of Differential Voltage (|VID|) Common-Mode Input Voltage (VIC) Input Voltage (VIN) Operating Temperature (TA) 100mV to VCC 0.05V to 2.35V 0 to VCC 3.0V to 3.6V
-65C to +150C
150C
-40C to +85C
10,000V 450V
Note 1: The "Absolute Maximum Ratings": are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol VTH VTL IIN II(OFF) VIH VIL VOH VOL IOZ VIK ICCZ ICC CIN COUT Parameter Differential Input Threshold HIGH Differential Input Threshold LOW Input Current Power-Off Input Current Input High Voltage (EN or EN) Input Low Voltage (EN or EN) Output HIGH Voltage Output LOW Voltage Disabled Output Leakage Current Input Clamp Voltage Disabled Power Supply Current Power Supply Current Input Capacitance Output Capacitance IOH = -100 A IOH = -8 mA IOH = 100 A IOL = 8 mA EN = 0.8 and EN* = 2V, VOUT = 3.6V or 0V IIK = -18 mA Receiver Disabled Receiver Enabled, (RIN+ = 1V and RIN- = 1.4V) or (RIN+ = 1.4V and RIN- = 1V) 3.5 6 -1.5 5 15 Test Conditions See Figure 1 and Table 1 See Figure 1 and Table 1 VIN = 0V or VCC VCC = 0V, VIN = 0V or 3.6V 2.0 GND VCC -0.2 2.4 0.2 0.5 20 -100 20 20 VCC + 1.0 0.8 Min Typ (Note 2) 100 Max Units mV mV A A V V V V A V mA mA pF pF
Note 2: All typical values are at TA = 25C and with VCC = 3.3V.
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FIN1048
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol tPLH tPHL tTLH tTHL tSK(P) tSK(LH) tSK(HL) tSK(PP) fMAX tZH tZL tHZ tLZ Parameter Propagation Delay LOW-to-HIGH Propagation Delay HIGH-to-LOW Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Pulse Skew |tPLH - tPHL| Channel-to-Channel Skew (Note 4) Part-to-Part Skew (Note 5) Maximum Operating Frequency (Note 6) LVTTL Output Enable Time from Z to HIGH LVTTL Output Enable Time from Z to LOW LVTTL Output Disable Time from HIGH to Z LVTTL Output Disable Time from LOW to Z RL = 1k, CL = 10 pF, See Figure 3 RL = 1k, CL = 10 pF, see Figure 1 and Figure 2 200 375 6.0 6.0 6.0 6.0 |VID| = 400 mV, CL = 10 pF, RL = 1k See Figure 1 and Figure 2 Test Conditions Min 1.0 1.0 0.7 0.7 Typ (Note 3) 2.5 2.5 1.2 1.2 0.4 0.3 1.0 Max Units ns ns ns ns ns ns ns MHz ns ns ns ns
Note 3: All typical values are at TA = 25C and with VCC = 3.3V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V. All channels switching in phase.
Note A: All differential input pulses have frequency = 10MHz, tR or tF = 1ns Note B: CL includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V) VIA 1.25 1.15 2.4 2.3 0.1 0 1.5 0.9 2.4 1.8 0.6 0 VIB 1.15 1.25 2.3 2.4 0 0.1 0.9 1.5 1.8 2.4 0 0.6 Resulting Differential Input Voltage (mA) VID 100 -100 100 -100 100 -100 600 -600 600 -600 600 -600 Resulting Common Mode Input Voltage (V) VIC 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3
3
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FIN1048
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms
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4
FIN1048
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
5
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FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com


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